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8303fs?avr?08/2013 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 125 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? high endurance, non-volatile memory segments ? 16k bytes of in-syst em, self-programmable flash program memory ? endurance: 10,000 write/erase cycles ? 256 bytes of in-system programmable eeprom ? endurance: 100,000 write/erase cycles ? 1k byte of internal sram ? data retention: 20 years at 85 ? c / 100 years at 25 ? c ? programming lock for self-progra mming flash & eeprom data security ? peripheral features ? dedicated hardware and qtouch ? library support for capacitive touch sensing ? one 8-bit and one 16-bit timer/counter with two pwm channels, each ? 12-channel, 10-bit adc ? programmable ultra low power watchdog timer ? on-chip analog comparator ? two full duplex usarts wit h start frame detection ? universal serial interface ? slave i 2 c serial interface ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi port ? internal and external interrupt sources ? pin change interrupt on 18 pins ? low power idle, adc noise reduction, standby and power-down modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit with supply voltage sampling ? calibrated 8mhz oscillator with temperature calibration option ? calibrated 32khz ultra low power oscillator ? on-chip temperature sensor ? i/o and packages ? 18 programmable i/o lines ? 20-pad qfn/mlf, and 20-pin soic ? operating voltage: ? 1.8 ? 5.5v ? speed grade: ? 0 ? 2mhz @ 1.8 ? 5.5v ? 0 ? 8mhz @ 2.7 ? 5.5v ? 0 ? 12mhz @ 4.5 ? 5.5v ? temperature range: -40 ? c to +85 ? c ? low power consumption ? active mode: 0.2ma at 1.8v and 1mhz ? idle mode: 30a at 1.8v and 1mhz ? power-down mode (wdt enabled): 1a at 1.8v ? power-down mode (wdt disabled): 100na at 1.8v 8-bit atmel tinyavr microcontroller with 16k bytes in-system programmable flash attiny1634 datasheet summary
2 attiny1634 [datasheet] 8303fs?avr?08/2013 1. pin configurations figure 1-1. pinout of attiny1634 1 2 3 4 5 qfn/mlf 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 note bottom pad should be soldered to ground. (pcint1/ain0) pa1 (pcint0/aref) pa0 gnd vcc pc5 (xtal1/clki/pcint17) pc0 (adc9/oc0a/xck0/pcint12) pc1 (adc10/icp1/scl/usck/xck1/pcint13) pc2 (adc11/clko/int0/pcint14) pc3 (reset/dw/pcint15) pc4 (xtal2/pcint16) pa7 (pcint7/rxd0/adc4) pb0 (pcint8/txd0/adc5) pb1 (adc6/di/sda/rxd1/pcint9) pb2 (adc7/do/txd1/pcint10) pb3 (adc8/oc1a/pcint11) (pcint6/oc1b/adc3) pa6 (pcint5/oc0b/adc2) pa5 (pcint4/t0/adc1) pa4 (pcint3/t1/sns/adc0) pa3 (pcint2/ain1) pa2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (pcint8/txd0/adc5) pb0 (pcint7/rxd0/adc4) pa7 (pcint6/oc1b/adc3) pa6 (pcint5/oc0b/adc2) pa5 (pcint4/t0/adc1) pa4 (pcint3/t1/sns/adc0) pa3 (pcint2/ain1) pa2 (pcint1/ain0) pa1 (pcint0/aref) pa0 gnd pb1 (adc6/di/sda/rxd1/pcint9) pb2 (adc7/do/txd1/pcint10) pb3 (adc8/oc1a/pcint11) pc0 (adc9/oc0a/xck0/pcint12) pc1 (adc10/icp1/scl/usck/xck1/pcint13) pc2 (adc11/clko/int0/pcint14) pc3 (reset/dw/pcint15) pc4 (xtal2/pcint16) pc5 (xtal1/clki/pcint17) vcc soic
3 attiny1634 [datasheet] 8303fs?avr?08/2013 1.1 pin descriptions 1.1.1 vcc supply voltage. 1.1.2 gnd ground. 1.1.3 xtal1 input to the inverting amplifie r of the oscillator and the inte rnal clock circuit. this is an alternative pin configuration of pc5. 1.1.4 xtal2 output from the inverting amp lifier of the oscillator. altern ative pin configuration of pc4. 1.1.5 reset reset input. a low le vel on this pin for longer than the minimum pulse le ngth will generate a reset, even if the clock is not running and provided the reset pin has not bee n disabled. the minimum pulse length is given in table 24-5 on page 231 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin. 1.1.6 port a (pa7:pa0) this is an 8-bit, bi-directional i/o po rt with internal pull-up resistors (selecte d for each bit). outp ut buffers have the following drive characteristics: ? pa7, pa4:pa0: symmetrical, with stan dard sink and source capability ? pa6, pa5: asymmetrical, with high si nk and standard source capability as inputs, port pins that are externally pulled low will s ource current provided that pull-up resistors are activated. port pins are tri-stated when a reset condition be comes active, even if th e clock is not running. this port has alternate pin functions to serve special features of the device. see ?alternate functions of port a? on page 62 . 1.1.7 port b (pb3:pb0) this is a 4-bit, bi-directional i/o port with internal pull-up resistors (selected for each bit).output buffers have the following drive characteristics: ? pb3: asymmetrical, with high sink and standard source capability ? pb2:pb0: symmetrical, with stan dard sink and source capability as inputs, port pins that are externally pulled low will s ource current provided that pull-up resistors are activated. port pins are tri-stated when a reset condition be comes active, even if th e clock is not running. this port has alternate pin functions to serve special features of the device. see ?alternate functions of port b? on page 65 . 1.1.8 port c (pc5:pc0) this is a 6-bit, bi-directional i/o port with internal pull-up resistors (selected for each bit). output buffers have the following drive characteristics:
4 attiny1634 [datasheet] 8303fs?avr?08/2013 ? pc5:pc1: symmetrical, with standar d sink and source capability ? pc0: asymmetrical, with high sink and standard source capability as inputs, port pins that are externally pulled low will s ource current provided that pull-up resistors are activated. port pins are tri-stated when a reset condition be comes active, even if th e clock is not running. this port has alternate pin functions to serve special features of the device. see ?alternate functions of port c? on page 67 . 2. overview attiny1634 is a low-power cmos 8-bit microcontrolle rs based on the avr enhanced risc architecture. by exe- cuting powerful instructions in a si ngle clock cycle, the attiny1634 achi eves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. figure 2-1. block diagram debug interface calibrated ulp oscillator watchdog timer calibrated oscillator timing and control v cc reset gnd 8-bit data bus cpu core program memory (flash) data memory (sram) power supervision: por bod reset isp interface port a port c port b voltage reference multiplexer analog comparator adc temperature sensor two-wire interface usart0 touch sensing eeprom on-chip debugger pc[5:0] pb[3:0] pa[7:0] 8-bit timer/counter 16-bit timer/counter usi usart1
5 attiny1634 [datasheet] 8303fs?avr?08/2013 the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. the resulting arch itecture is compact and code efficient while achieving throughputs up to ten times faster th an conventional cisc microcontrollers. attiny1634 provides the following features: ? 16k bytes of in-system programmable flash ? 1k bytes of sram data memory ? 256 bytes of eeprom data memory ? 18 general purpose i/o lines ? 32 general purpose working registers ? an 8-bit timer/counter with two pwm channels ? a16-bit timer/counter with two pwm channels ? internal and external interrupts ? a 10-bit adc with 5 internal and 12 external channels ? an ultra-low power, programmable wa tchdog timer with internal oscillator ? two programmable usart?s with start frame detection ? a slave two-wire interface (twi) ? a universal serial interface (usi) with start condition detector ? a calibrated 8m hz oscillator ? a calibrated 32khz, ul tra low power oscillator ? four software selectable power saving modes. the device includes the following modes for saving power: ? idle mode: stops the cpu while allo wing the timer/counter, adc, analog comparator, spi, twi, and interrupt system to continue functioning ? adc noise reduction mode: minimizes switching noise during adc conversions by stopping the cpu and all i/o modules except the adc ? power-down mode: registers keep their contents and all ch ip functions are disabled until the next interrupt or hardware reset ? standby mode: the oscillator is running while the rest of the device is sl eeping, allowing very fast start-up combined with low power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the flash program mem- ory can be re-programmed in-system through a serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code, running on the avr core. the attiny1634 avr is supported by a full suite of prog ram and system development tools including: c compilers, macro assemblers, program debugger/simulators and evaluation kits.
6 attiny1634 [datasheet] 8303fs?avr?08/2013 3. general information 3.1 resources a comprehensive set of drivers, application notes, data s heets and descriptions on dev elopment tools are available for download at http:/ /www.atmel.com/avr. 3.2 code examples this documentation contains simple co de examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compile r documentation for more details. for i/o registers located in the extended i/o map, ?in?, ?o ut?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typica lly, this means ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?c br?. note that not all avr devices include an extended i/o map. 3.3 capacitive touch sensing atmel qtouch library provides a simple to use solution for touch sensitive interfac es on atmel avr microcon- trollers. the qtouch library includes support for qtouch ? and qmatrix ? acquisition methods. touch sensing is easily added to any application by linki ng the qtouch library and using the application program- ming interface (api) of the library to define the touch channels and sensors. the applicati on then calls the api to retrieve channel information and determine the state of the touch sensor. the qtouch library is free and can be downloaded from the atmel website. for more information and details of implementation, refer to the qtouch library user guide ? also available from the atmel website. 3.4 data retention reliability qualification results show that the projected data retention failure ra te is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 4. cpu core this section discusses the avr core ar chitecture in general. the main function of the cpu core is to ensure cor- rect program execution. the cpu mu st therefore be able to access memo ries, perform calculations, control peripherals, and handle interrupts.
7 attiny1634 [datasheet] 8303fs?avr?08/2013 5. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page(s) (0xff)reserved???????? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? ... ... ... ... ... ... ... ... ... ... ... (0x85) reserved ? ? ? ? ? ? ? ? (0x84) reserved ? ? ? ? ? ? ? ? (0x83) reserved ? ? ? ? ? ? ? ? (0x82) reserved ? ? ? ? ? ? ? ? (0x81) reserved ? ? ? ? ? ? ? ? (0x80) reserved ? ? ? ? ? ? ? ? (0x7f) twscra twshe ? twdie twasie twen twsie twpme twsme 127 (0x7e) twscrb twaa twcmd[1:0] 127 (0x7d) twssra twdif twasif twch twra twc twbe twdir twas 128 (0x7c) twsa twi slave address register 130 (0x7b) twsam twi slave address mask register 130 (0x7a) twsd twi slave data register 130 (0x79) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 167 (0x78) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 168 (0x77) ucsr1c umsel11 umsel10 upm11 upm01 usbs1 ucsz11 ucsz10 ucpol1 169 (0x76) ucsr1d rxsie1 rxs1 sfde1 171 (0x75) ubrr1h usart1 baud rate register high byte 172 (0x74) ubrr1l usart1 baud rate register low byte 172 (0x73) udr1 usart1 i/o data register 167 (0x72) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 111 (0x71) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 113 (0x70) tccr1c foc1a foc1b ? ? ? ? ? ? 114 (0x6f) tcnt1h timer/counter1 ? counter register high byte 114 (0x6e) tcnt1l timer/counter1 ? counter register low byte 114 (0x6d) ocr1ah timer/counter1 ? compare register a high byte 114 (0x6c) ocr1al timer/counter1 ? compare register a low byte 114 (0x6b) ocr1bh timer/counter1 ? compare register b high byte 115 (0x6a) ocr1bl timer/counter1 ? compare register b low byte 115 (0x69) icr1h timer/counter1 ? input capture register high byte 115 (0x68) icr1l timer/counter1 ? input capture register low byte 115 (0x67) gtccr tsm ? ? ? ? ? ? psr10 118 (0x66) osccal1 ? ? ? ? ? ?cal11cal10 33 (0x65) osctcal0b oscillator temperature compensation register b 33 (0x64) osctcal0a oscillator temperature compensation register a 33 (0x63) osccal0 cal07 cal06 cal05 cal04 cal03 cal02 cal01 cal00 32 (0x62) didr2 ? ? ? ? ? adc11d adc10d adc9d 200 (0x61) didr1 ? ? ? ? adc8d adc7d adc6d adc5d 200 (0x60) didr0 adc4d adc3d adc2d adc1d adc0d ain1d ain0d arefd 184 , 200 0x3f (0x5f) sreg i t h s v n z c 14 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 13 0x3c (0x5c) gimsk ? int0 pcie2 pcie1 pcie0 ? ? ? 51 0x3b (0x5b) gifr ? intf0 pcif2 pcif1 pcif0 ? ? ? 52 0x3a (0x5a) timsk toie1 ocie1a ocie1b ? icie1 ocie0b toie0 ocie0a 88 , 115 0x39 (0x59) tifr tov1 ocf1a ocf1b ? icf1 ocf0b tov0 ocf0a 89 , 116 0x38 (0x58) qtcsr qtouch control and status register 6 0x37 (0x57) spmcsr ? ? rsig ctpb rflb pgwrt pgers spmen 207 0x36 (0x56) mcucr ?sm1sm0se ? ?isc01isc00 37 , 51 0x35 (0x55) mcusr ? ? ? ? wdrf borf extrf porf 44 0x34 (0x54) prr ? prtwi prtim0 prtim0 prusi prusart1 prusart0 pradc 38 0x33 (0x53) clkpr ? ? ? ? clkps3 clkps2 clkps1 clkps0 31 0x32 (0x52) clksr oscrdy cstr ckout_io sut cksel3 cksel2 cksel1 cksel0 29 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) wdtcsr wdif wdie wdp3 ? wde wdp2 wdp1 wdp0 45 0x2f (0x4f) ccp cpu change protection register 13 0x2e (0x4e) dwdr dwdr[7:0] 202 0x2d (0x4d) usibr usi buffer register 144 0x2c (0x4c) usidr usi data register 143
8 attiny1634 [datasheet] 8303fs?avr?08/2013 note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accesse d. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specif ied bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 0x2b (0x4b) usisr usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 142 0x2a (0x4a) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 140 0x29 (0x49) pcmsk2 ? ? pcint17 pcint16 pcint15 pcint14 pcint13 pcint12 52 0x28 (0x48) pcmsk1 ? ? ? ? pcint11 pcint10 pcint9 pcint8 53 0x27 (0x47) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 53 0x26 (0x46) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm 167 0x25 (0x45) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 168 0x24 (0x44) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 169 0x23 (0x43) ucsr0d rxcie0 rxs0 sfde0 ? ? ? ? ? 171 0x22 (0x42) ubrr0h ? ? ? ? usart0 baud rate register high byte 172 0x21 (0x41) ubrr0l usart0 baud rate register low byte 172 0x20 (0x40) udr0 usart0 i/o data register 167 0x1f (0x3f) eearh ? ? ? ? ? ? ? ? 0x1e (0x3e) eearl eear[7:0] 22 0x1d (0x3d) eedr eeprom data register 22 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 22 0x1b (0x3b) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 84 0x1a (0x3a) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 86 0x19 (0x39) tcnt0 timer/counter0 88 0x18 (0x38) ocr0a timer/counter0 ? compare register a 88 0x17 (0x37) ocr0b timer/counter0 ? compare register b 88 0x16 (0x36) gpior2 general purpose register 2 23 0x15 (0x35) gpior1 general purpose register 1 24 0x14 (0x34) gpior0 general purpose register 0 24 0x13 (0x33) portcr ? ? ? ? ? bbmc bbmb bbma 71 0x12 (0x32) puea puea7 puea6 puea5 puea4 puea3 puea2 puea1 puea0 71 0x11 (0x31) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 71 0x10 (0x30) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 71 0x0f (0x2f) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 71 0x0e (0x2e) pueb ? ? ? ? pueb3 pueb2 pueb1 pueb0 72 0x0d (0x2d) portb ? ? ? ? portb3 portb2 portb1 portb0 72 0x0c (0x2c) ddrb ? ? ? ? ddb3 ddb2 ddb1 ddb0 72 0x0b (0x2b) pinb ? ? ? ? pinb3 pinb2 pinb1 pinb0 72 0x0a (0x2a) puec ? ? puec5 puec4 puec3 puec2 puec1 puec0 72 0x09 (0x29) portc ? ? portc5 portc4 portc3 portc2 portc1 portc0 72 0x08 (0x28) ddrc ? ? ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 72 0x07 (0x27) pinc ? ? pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 72 0x06 (0x26) acsra acd acbg aco aci acie acic acis1 acis0 182 0x05 (0x25) acsrb hsel hlev aclp ? acce acme acirs1 acirs0 183 0x04 (0x24) admux refs1 refs0 refen adc0en mux3 mux2 mux1 mux0 196 0x03 (0x23) adcsra aden adsc adate adif adie adps2 adps1 adps0 197 0x02 (0x22) adcsrb vden vdpd ? ? adlar adts2 adts1 adts0 199 0x01 (0x21) adch adc data register high byte 198 0x00 (0x20) adcl adc data register low byte 198 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page(s)
9 attiny1634 [datasheet] 8303fs?avr?08/2013 6. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd ? rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd ? rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl ? rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd ? rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd ? rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd ? rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd ? rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl ? rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd ?? rd ? rr z,n,v 1 andi rd, k logical and register and constant rd ? rd ?? k z,n,v 1 or rd, rr logical or registers rd ? rd v rr z,n,v 1 ori rd, k logical or register and constant rd ?? rd v k z,n,v 1 eor rd, rr exclusive or registers rd ? rd ? rr z,n,v 1 com rd one?s complement rd ? 0xff ? rd z,c,n,v 1 neg rd two?s complement rd ? 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd ? rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd ? rd ? (0xff - k) z,n,v 1 inc rd increment rd ? rd + 1 z,n,v 1 dec rd decrement rd ? rd ? 1 z,n,v 1 tst rd test for zero or minus rd ? rd ? rd z,n,v 1 clr rd clear register rd ? rd ? rd z,n,v 1 ser rd set register rd ? 0xff none 1 branch instructions jmp k direct jump pc ? knone3 rjmp k relative jump pc ?? pc + k + 1 none 2 ijmp indirect jump to (z) pc ? z none 2 call k direct subroutine pc ? knone4 rcall k relative subroutine call pc ? pc + k + 1 none 3 icall indirect call to (z) pc ? znone3 ret subroutine return pc ? stack none 4 reti interrupt return pc ? stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc ?? pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc ? pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc ? pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n ? v= 1) then pc ? pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc ? pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc ? pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) ? 1none2 cbi p,b clear bit in i/o register i/o(p,b) ? 0none2 lsl rd logical shift left rd(n+1) ? rd(n), rd(0) ? 0 z,c,n,v 1 lsr rd logical shift right rd(n) ? rd(n+1), rd(7) ? 0 z,c,n,v 1 rol rd rotate left through carry rd(0) ? c,rd(n+1) ? rd(n),c ? rd(7) z,c,n,v 1
10 attiny1634 [datasheet] 8303fs?avr?08/2013 ror rd rotate right through carry rd(7) ? c,rd(n) ? rd(n+1),c ? rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4),rd(7..4) ? rd(3..0) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? tnone1 sec set carry c ? 1c1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1n1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1z1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1i1 cli global interrupt disable i ?? 0 i 1 ses set signed test flag s ? 1s1 cls clear signed test flag s ? 0 s 1 sev set twos complement overflow. v ? 1v1 clv clear twos complement overflow v ? 0 v 1 set set t in sreg t ? 1t1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1h1 clh clear half carry flag in sreg h ? 0 h 1 data transfer instructions mov rd, rr move between registers rd ? rr none 1 movw rd, rr copy register word rd+1:rd ? rr+1:rr none 1 ldi rd, k load immediate rd ? knone1 ld rd, x load indirect rd ? (x) none 2 ld rd, x+ load indirect and post-inc. rd ? (x), x ? x + 1 none 2 ld rd, - x load indirect and pre-dec. x ? x - 1, rd ? (x) none 2 ld rd, y load indirect rd ? (y) none 2 ld rd, y+ load indirect and post-inc. rd ? (y), y ? y + 1 none 2 ld rd, - y load indirect and pre-dec. y ? y - 1, rd ? (y) none 2 ldd rd,y+q load indirect with displacement rd ? (y + q) none 2 ld rd, z load indirect rd ? (z) none 2 ld rd, z+ load indirect and post-inc. rd ? (z), z ? z+1 none 2 ld rd, -z load indirect and pre-dec. z ? z - 1, rd ? (z) none 2 ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 lds rd, k load direct from sram rd ? (k) none 2 st x, rr store indirect (x) ?? rr none 2 st x+, rr store indirect and post-inc. (x) ?? rr, x ? x + 1 none 2 st - x, rr store indirect and pre-dec. x ? x - 1, (x) ? rr none 2 st y, rr store indirect (y) ? rr none 2 st y+, rr store indirect and post-inc. (y) ? rr, y ? y + 1 none 2 st - y, rr store indirect and pre-dec. y ? y - 1, (y) ? rr none 2 std y+q,rr store indirect with displacement (y + q) ? rr none 2 st z, rr store indirect (z) ? rr none 2 st z+, rr store indirect and post-inc. (z) ? rr, z ? z + 1 none 2 st -z, rr store indirect and pre-dec. z ? z - 1, (z) ? rr none 2 std z+q,rr store indirect with displacement (z + q) ? rr none 2 sts k, rr store direct to sram (k) ? rr none 2 lpm load program memory r0 ? (z) none 3 lpm rd, z load program memory rd ? (z) none 3 lpm rd, z+ load program memory and post-inc rd ? (z), z ? z+1 none 3 spm store program memory (z) ? r1:r0 none in rd, p in port rd ? pnone1 out p, rr out port p ? rr none 1 push rr push register on stack stack ? rr none 2 pop rd pop register from stack rd ? stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
11 attiny1634 [datasheet] 8303fs?avr?08/2013 7. ordering information notes: 1. for speed vs. supply voltage, see section 24.3 ?speed? on page 229 . 2. all packages are pb-free, halide-free and fully green, and they comply with the eur opean directive for restriction of hazard- ous substances (rohs). 3. denotes accuracy of the internal oscillator. see table 24-2 on page 230 . 4. code indicators: ? u: matte tin ? r: tape & reel 5. can also be supplied in wafer form. contact your local atmel sales office for ordering information and minimum quantities. 7.1 attiny1634 speed (mhz) (1) supply voltage (v) temperature range package (2) accuracy (3) ordering code (4) 12 1.8 ? 5.5 industrial (-40 ? c to +85 ? c) (5) 20m1 10% attiny1634-mu 2% attiny1634r-mu 10% ATTINY1634-MUR 2% attiny1634r-mur 20s2 10% attiny1634-su 2% attiny1634r-su 10% attiny1634-sur 2% attiny1634r-sur 20u-1 10% attiny1634-uur package type 20m1 20-pad, 4 x 4 x 0.8 mm body, quad flat no- lead / micro lead frame package (qfn/mlf) 20s2 20-lead, 0.300" wide body, plastic gull wing small outline package (soic) 20u-1 20-ball 2.38 x 2.02 x 0.409mm body, 5x4 array, 0.40 mm pitch, wafer level chip scale package (wlcsp)
12 attiny1634 [datasheet] 8303fs?avr?08/2013 8. packaging information 8.1 20m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20m1 , 20-pad, 4 x 4 x 0.8 mm body, lead pitch 0.50 mm, b 20m1 10/27/04 2.6 mm exposed pad, micro lead frame package (mlf) a 0.70 0.75 0.80 a1 ? 0.01 0.05 a2 0.20 ref b 0.18 0.23 0.30 d 4.00 bsc d2 2.45 2.60 2.75 e 4.00 bsc e2 2.45 2.60 2.75 e 0.50 bsc l 0.35 0.40 0.55 side view pin 1 id pin #1 notch (0.20 r) bottom view top view note: reference jedec standard mo-220, fig . 1 (saw singulation) wggd-5. common dimensions (unit of measure = mm) symbol min nom max note d e e a2 a1 a d2 e2 0.08 c l 1 2 3 b 1 2 3
13 attiny1634 [datasheet] 8303fs?avr?08/2013 8.2 20s2
14 attiny1634 [datasheet] 8303fs?avr?08/2013 8.3 20u-1
15 attiny1634 [datasheet] 8303fs?avr?08/2013 9. errata the revision letters in this sect ion refer to the revision of the corresponding attiny1634 device. 9.1 attiny1634 9.1.1 rev. b ? port pin should not be used as input when ulp oscillator is disabled 1. port pin should not be used as input when ulp oscillator is disabled port pin pb3 is not guarant eed to perform as a reliable input when the ultra low power (ulp) oscillator is not running. in addition, the pin is pulled down internally when ulp oscillator is disabled. problem fix / workaround the ulp oscillator is automatically activated when required. to use pb 3 as an input, activate the watchdog timer. the watchdog timer automa tically enables the ulp oscillator. 9.1.2 rev. a ? flash / eeprom can not be written wh en supply voltag e is below 2.4v ? port pin should not be used as input when ulp oscillator is disabled 1. flash / eeprom can not be written when supply voltage is below 2.4v when supply voltage is below 2.4v write operations to flash and eeprom may fail. problem fix / workaround do not write to flash or eeprom wh en supply voltage is below 2.4v. 2. port pin should not be used as input when ulp oscillator is disabled port pin pb3 is not guarant eed to perform as a reliable input when the ultra low power (ulp) oscillator is not running. in addition, the pin is pulled down internally when ulp oscillator is disabled. problem fix / workaround the ulp oscillator is automatically activated when required. to use pb 3 as an input, activate the watchdog timer. the watchdog timer automa tically enables the ulp oscillator.
16 attiny1634 [datasheet] 8303fs?avr?08/2013 10. datasheet revision history 10.1 rev. 8303f ? 08/2013 1. updated bit 2 from the ucsr1c regist er from ?usbsz11? to ?ucsz11? in ?register summary? on page 7 . 10.2 rev. 8303e ? 01/2013 1. updated: ? applied the atmel new brand template that includes new log and new addresses. 10.3 rev. 8303d ? 06/12 1. updated: ? ?ordering information? on page 11 2. added: ? wafer level chip scale package ?20u-1? on page 14 10.4 rev. 8303c ? 03/12 1. updated: ? ?register description? on page 167 ? ?self-programming? on page 203 10.5 rev. 8303b ? 03/12 1. removed preliminary status. 2. added: ? ?typical characteristics? on page 239 ? ?temperature sensor? on page 235 ? ?rev. b? on page 15 3. updated: ? ?pin descriptions? on page 3 ? ?calibrated internal 8mhz oscillator? on page 27 ? ?osctcal0a ? oscillator temperature calibration register a? on page 33 ? ?osctcal0b ? oscillator temperature calibration register b? on page 33 ? ?twscra ? twi slave control register a? on page 127 ? ?usart (usart0 & usar t1)? on page 145 ? ?temperature vs. sensor output voltage (typical)? on page 195 ? ?dc characteristics? on page 228 ? ?calibration accuracy of internal 32khz oscillator? on page 231 ? ?external clock drive characteristics? on page 231 ? ?reset, brown-out, and internal voltage characteristics? on page 231 ? ?analog comparator characteristics, ta = -40c to +85c? on page 235 ? ?parallel programming characteristics, t a = 25 ? c, v cc = 5v? on page 237 ? ?serial programming characteristics, t a = -40c to +85c? on page 238 ? ?ordering information? on page 11
17 attiny1634 [datasheet] 8303fs?avr?08/2013 10.6 rev. 8303a ? 11/11 initial revision.
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 8303fs?avr?08/2013 disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , avr ? , tinyavr ? , qtouch ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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